基于FPGA的AD7705输入设计VHDL代码Quartus仿真

名称：基于FPGA的AD7705输入设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

AD7705输入,(4000-输入)/7(仿真输出=学号后3位),8位∪ART发送输出。

每位交一个pdf文档,联系应用井至少比较一种不同方案进行方案分析。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. RTL图

5. 仿真图

AD7705模块仿真

--042=(4000-x)/7

--x=3706

--==0000111001111010

数据拆分模块仿真

分频模块

UART发送模块

部分代码展示:

-042=(4000-x)/7
--x=3706
--==0000111001111010
LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
USE?ieee.std_logic_arith.all;
--AD7705驱动
ENTITY?AD7705_driver?IS
???PORT?(
??????clk_in????????????????:?IN?STD_LOGIC;
??????reset_n????????????????:?IN?STD_LOGIC;--系统复位信号，低有效
??????AD_data_out????????????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0);--输出AD数据
??????AD_DRDY_n??????????????:?IN?STD_LOGIC;--AD7705
??????AD_dout????????????????:?IN?STD_LOGIC;--AD7705
??????AD_CS??????????????????:?OUT?STD_LOGIC;--AD7705
??????AD_clk?????????????????:?OUT?STD_LOGIC;--AD7705
??????AD_din?????????????????:?OUT?STD_LOGIC--AD7705
???);
END?AD7705_driver;
ARCHITECTURE?behave?OF?AD7705_driver?IS
???type?state_type?is(
??????s_reset????????????????,--FFFF
??????s_communicate_clkreg???,--8'h20
??????s_clk_reg??????????????,--8'h03
??????s_communicate_setreg???,--8'h10
??????s_set_reg??????????????,--8'h40
??????s_communicate_datareg??,--8'h38,读通道1
??????s_read_data????????????,--读数16bit
??????s_wait_DRDY?????????????--等待DRDY==0
???);
???SIGNAL?state?:state_type:=s_reset;???
???--定义寄存器
???SIGNAL?communicate_clkreg??:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00100000";
???SIGNAL?clk_reg?????????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000011";
???SIGNAL?communicate_setreg??:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00010000";
???SIGNAL?set_reg?????????????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"01000000";
???SIGNAL?communicate_datareg?:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00111000";
???
???SIGNAL?cycle_cnt???????????:?integer?:=?0;
???SIGNAL?AD_clk_reg??????????:?STD_LOGIC?:=?'0';
???SIGNAL?AD_clk_reg_cnt??????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
???SIGNAL?clk_en??????????????:?STD_LOGIC?:=?'0';
???SIGNAL?AD_din_reg??????????:?STD_LOGIC?:=?'0';
???SIGNAL?AD_clk_reg_buf??????:?STD_LOGIC?:=?'0';
???SIGNAL?AD_clk_reg_down?????:?STD_LOGIC;
???SIGNAL?AD_clk_reg_rise?????:?STD_LOGIC;
???
???SIGNAL?AD_data?????????????:?STD_LOGIC_VECTOR(15?DOWNTO?0)?:=?"0000000000000000";
SIGNAL?result??:?INTEGER?:=?0;?--计算结果
BEGIN
???AD_CS?<=?'0';--CS保持低电平
???
???--AD_clk最大5M，上升沿读写
???PROCESS?(clk_in)
???BEGIN
??????IF?(clk_in'EVENT?AND?clk_in?=?'1')?THEN
?????????IF?(reset_n?=?'0')?THEN
????????????AD_clk_reg_cnt?<=?"00000000";
?????????ELSIF?(AD_clk_reg_cnt?=?"00001001")?THEN--使用5M时钟,50/5=10;
????????????AD_clk_reg_cnt?<=?"00000000";
?????????ELSE
????????????AD_clk_reg_cnt?<=?AD_clk_reg_cnt?+?"00000001";
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???--50M分频为5MHz
???PROCESS?(clk_in)
???BEGIN
??????IF?(clk_in'EVENT?AND?clk_in?=?'1')?THEN
?????????IF?(AD_clk_reg_cnt?>=?"00000101")?THEN
????????????AD_clk_reg?<=?'1';
?????????ELSE
????????????AD_clk_reg?<=?'0';
?????????END?IF;
??????END?IF;
???END?PROCESS;
???
???AD_clk?<=?AD_clk_reg?AND?clk_en;--5M
???AD_din?<=?AD_din_reg?AND?clk_en;
???PROCESS?(clk_in)
???BEGIN
??????IF?(clk_in'EVENT?AND?clk_in?=?'1')?THEN
?????????AD_clk_reg_buf?<=?AD_clk_reg;
??????END?IF;
???END?PROCESS;
???
???AD_clk_reg_down?<=?NOT(AD_clk_reg)?AND?AD_clk_reg_buf;--AD_clk_reg的下降沿
???AD_clk_reg_rise?<=?AD_clk_reg?AND?NOT(AD_clk_reg_buf);--AD_clk_reg的上升沿
???
???--初始化及读取AD值状态机
???PROCESS?(clk_in)
???BEGIN
??????IF?(clk_in'EVENT?AND?clk_in?=?'1')?THEN
?????????IF?(reset_n?=?'0')?THEN
????????????state?<=?s_reset;
????????????cycle_cnt?<=?0;
????????????clk_en?<=?'0';
????????????communicate_clkreg?<=?"00100000";
????????????clk_reg?<=?"00000011";
????????????communicate_setreg?<=?"00010000";
????????????set_reg?<=?"01000000";
????????????communicate_datareg?<=?"00111000

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=767