数字钟VHDL电子时钟DE1-SOC开发板数字时钟报时_电路方案

名称：数字钟VHDL电子时钟DE1-SOC开发板数字时钟（代码在文末下载）

软件：Quartus II

语言：VHDL

代码功能：

1、设计数字钟功能，可以通过数码管显示时分秒。

2、可以通过按键修改小时、分钟。

3、具有整点报时功能。

本代码已在DE1-SOC开发板验证，开发板如下，其他开发板可以修改管脚适配：

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
--数字钟
ENTITY?Digital_clock_A111417?IS
???PORT?(
??????clk_in????:?IN?STD_LOGIC;--50MHz
??????bell_out???:?OUT?STD_LOGIC;--整点报时蜂鸣器，BELL?当?I/O15?为低电平时?BELL?发出嘟嘟的声音
key_hour???:?IN?STD_LOGIC;--修改小时
key_minute?:?IN?STD_LOGIC;--修改分钟
??????--6个数码管
??????HEX0???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX1???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX2???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX3???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX4???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX5???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0)
???);
END?Digital_clock_A111417;
ARCHITECTURE?trans?OF?Digital_clock_A111417?IS
--模块声明
???COMPONENT?Bell?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
?????????hour_time??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????bell_out???:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
--数码管显示模块
COMPONENT?HEX?IS
???PORT?(
??????clk????:?IN?STD_LOGIC;
??????hour_time??????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--时
??????minute_time????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--分
??????second_time????????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--秒
??????--6个数码管
??????HEX0???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX1???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX2???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX3???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX4???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0);
??????HEX5???:?OUT?STD_LOGIC_VECTOR(6?DOWNTO?0)
???);
END?COMPONENT;
???
???COMPONENT?fenping?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
?????????clk_1Hz????:?OUT?STD_LOGIC
??????);
???END?COMPONENT;
???
???COMPONENT?jishi?IS
??????PORT?(
?????????clk_in????:?IN?STD_LOGIC;
key_hour???:?IN?STD_LOGIC;--修改小时
key_minute?:?IN?STD_LOGIC;--修改分钟
?????????clk_1Hz????:?IN?STD_LOGIC;
?????????hour_time??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????minute_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????second_time?:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???
???SIGNAL?hour_time?????????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?minute_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?second_time???????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???
???SIGNAL?clk_1Hz???????????:?STD_LOGIC;
BEGIN
???--分频到1Hz
???fenping_Hz?:?fenping
??????PORT?MAP?(
?????????clk_in??=>?clk_in,
?????????clk_1Hz??=>?clk_1Hz
??????);
???
???
???--计时模块
???i_jishi?:?jishi
??????PORT?MAP?(
?????????clk_in??????=>?clk_in,
key_hour=>?key_hour,---修改小时
key_minute=>?key_minute,---修改分钟
?????????clk_1Hz??????=>?clk_1Hz,
?????????hour_time????=>?hour_time,--时
?????????minute_time??=>?minute_time,--分
?????????second_time??=>?second_time--秒
??????);
???--响铃模块
???i_Bell?:?Bell
??????PORT?MAP?(
?????????clk_in????????????=>?clk_in,
?????????
?????????hour_time??????????=>?hour_time,--时
?????????minute_time????????=>?minute_time,--分
?????????second_time????????=>?second_time,--秒
?????????
?????????bell_out???????????=>?bell_out--闹钟led
??????);
??
--数码管显示模块
?i_HEX:?HEX
???PORT?MAP??(
??????clk=>?clk_in,
??????hour_time=>hour_time,--时
??????minute_time=>minute_time,--分
??????second_time=>second_time,--秒
??????--6个数码管
??????HEX0=>HEX0,
??????HEX1=>HEX1,
??????HEX2=>HEX2,
??????HEX3=>HEX3,
??????HEX4=>HEX4,
??????HEX5=>HEX5
???);
???
END?trans;

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