基于FPGA的扩频信号及BPSK调制信号产生VHDL代码ISE仿真

名称：基于FPGA的扩频信号及BPSK调制信号产生VHDL代码ISE仿真

软件：ISE

语言：VHDL

代码功能：

扩频信号及BPSK调制信号产生

通过此次课程设计，使同学们可以掌握扩频信号产生机理，掌握ISE软件的使用方法，了解基于FPGA的数字电路设计和开发方法。

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1.工程文件

2.程序文件

3.程序编译

4.Testbench

5.仿真图

整体仿真图

GOLD码产生模块仿真图

DDS模块仿真图

延迟单时钟周期寄存器模块仿真图

部分代码展示:

library?IEEE;
use?IEEE.STD_LOGIC_1164.ALL;
use?IEEE.STD_LOGIC_ARITH.ALL;
use?IEEE.STD_LOGIC_UNSIGNED.ALL;
--BPSK调制信号产生模块
entity?CAcode_bpsk?is
????Port?(?clk?:?in??STD_LOGIC;
???????????reset?:?in??STD_LOGIC;
???enable?:?in?std_logic;
???sv_num?:?in?std_logic_VECTOR?(5?downto?0);
???????????cacode_out?:?out??STD_LOGIC;
???????????ca_bpsk_out?:?out??STD_LOGIC_VECTOR?(5?downto?0));
end?CAcode_bpsk;
architecture?Behavioral?of?CAcode_bpsk?is
component?CACodeGenerator?is?????
?Port?(?
?????????CLKIN:in?STD_LOGIC;????????????????--10.23M
?????????RESET:in?STD_LOGIC;
??EN?:in?STD_LOGIC;
???????????Phase_S_L:in?STD_LOGIC_VECTOR(5?DOWNTO?0);??????
????????CA_OUT?:out??STD_LOGIC;
??CA_OUT_EN?:?out?STD_LOGIC?
??);
????end?component;
component?dds?IS
???PORT?(
??????CLK?:?IN?STD_LOGIC;
??????SINE?:?OUT?STD_LOGIC_VECTOR(5?DOWNTO?0)???
);
end?component;
component?Dregist?is
????Port?(?clk?:?in??STD_LOGIC;
???????????datain?:?in??STD_LOGIC;
???????????dataout?:?out??STD_LOGIC);
end?component;
signal?ca_out_en?:?std_logic;
signal?ca_out?:?std_logic;
signal?sine_out?:?std_logic_vector(5?downto?0);
signal?clk_128_out_a?:?std_logic;
signal?ca_out1?:std_logic;
signal?ca_out2?:std_logic;
signal?ca_out3?:std_logic;
begin
cacode_out?<=?ca_out;
U1?:?CACodeGenerator?????
?Port??map?(?
?????????CLKIN=>clk,????????????????--10.23M
?????????RESET=>reset,
??EN?=>?enable,??
???????????Phase_S_L=>?sv_num,????
????????CA_OUT?=>ca_out,
??CA_OUT_EN?=>?ca_out_en?
??);
U2?:?dds
port?map(
?????clk?=>?clk,
??sine?=>?sine_out?
??);
?u3?:?Dregist
?port?map(
?????clk?=>?clk,
??datain?=>?ca_out,?
??dataout?=>?ca_out1
??);

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=823