TFT-LCD时序接口驱动设计VHDL代码Quartus仿真

名称：TFT-LCD时序接口驱动设计VHDL代码Quartus仿真

软件：Quartus

语言：VHDL

代码功能：

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. 仿真文件

5. 仿真图

定义的HSPW为3，所以高电平为4个时钟

部分代码展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
???USE?ieee.std_logic_unsigned.all;
ENTITY?lcd_lcd?IS
???PORT?(
??????sclk_25M??:?IN?STD_LOGIC;--25M时钟
??????n_rst?????:?IN?STD_LOGIC;--低电平复位
??????hsync?????:?OUT?STD_LOGIC;--水平同步信号
??????vclk??????:?OUT?STD_LOGIC--视频时钟
???);
END?lcd_lcd;
ARCHITECTURE?RTL?OF?lcd_lcd?IS
???constant???s_init????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";--状态机的状态0
???constant???s_high????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0001";--状态机的状态1
???constant???s_low?????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0010";--状态机的状态2
???
???SIGNAL?hspw??????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000011";--3
???SIGNAL?hbpd??????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000100";--4
???SIGNAL?hozval????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00001111";--15
???SIGNAL?hfpd??????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000010";--2
???SIGNAL?ss????????:?STD_LOGIC_VECTOR(3?DOWNTO?0)?:=?"0000";--状态机的状态
???SIGNAL?cnt???????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";--用于计数的计数器
???SIGNAL?vclk_buf??:?STD_LOGIC?:=?'0';--缓存vclk
???SIGNAL?hsync_buf?:?STD_LOGIC?:=?'0';--缓存hsync
SIGNAL?add_all??????:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";--累加和
BEGIN
???
add_all<=hspw+"00000001"?+?hbpd+"00000001"??+?hozval+"00000001"??+?hfpd?+"00000001";--累加
???PROCESS?(vclk_buf,?n_rst)??--状态机，分为3个状态，初始状态s_init；高电平状态s_high；低电平状态s_low
???BEGIN
??????IF?((NOT(n_rst))?=?'1')?THEN
?????????ss?<=?s_init;--初始状态
??????ELSIF?(vclk_buf'EVENT?AND?vclk_buf?=?'1')?THEN
?????????CASE?ss?IS
????????????WHEN?s_init?=>--初始状态s_init
???????????????ss?<=?s_high;??????????????
????????????WHEN?s_high?=>--高电平状态s_high
???????????????IF?(cnt?=?hspw)?THEN--计数到hspw后跳转
??????????????????ss?<=?s_low;
???????????????ELSE
??????????????????ss?<=?s_high;
???????????????END?IF;
????????????WHEN?s_low?=>--低电平状态s_low
???????????????IF?(cnt?=??add_all?-"00000001")?THEN--计数到最大值后跳转
??????????????????ss?<=?s_high;
???????????????ELSE
??????????????????ss?<=?s_low;
???????????????END?IF;
????????????WHEN?OTHERS?=>
???????????????ss?<=?s_init;
?????????END?CASE;
??????END?IF;
???END?PROCESS;
???
???
???PROCESS?(vclk_buf,?n_rst)?--状态机的跳转依赖于cnt的计数值
???BEGIN
??????IF?((NOT(n_rst))?=?'1')?THEN
?????????cnt?<=?"00000000";
??????ELSIF?(vclk_buf'EVENT?AND?vclk_buf?=?'1')?THEN
?????????IF?(cnt?=??add_all?-"00000001")?THEN--计数到最大值后回零，循环计数
????????????cnt?<=?"00000000";
?????????ELSIF(ss=s_high?or?ss=s_low)THEN
????????????cnt?<=?cnt?+?"00000001";--计数
?????????END?IF;
??????END?IF;
???END?PROCESS;

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=983