串行并行数据转换模块设计Verilog代码VIVADO仿真

名称：串行并行数据转换模块设计Verilog代码VIVADO仿真

软件：VIVADO

语言：Verilog

代码功能：

1、串行数据转换为并行数据

2、并行数据转换为串行数据

3、并行数据为8位

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. Testbench

4. 仿真图

串转并仿真图

并转串仿真图

整体仿真图

部分代码展示:

`timescale?1ns?/?1ps
//////////////////////////////////////////////////////////////////////////////////
//?Company:?
//?Engineer:?
//?
//?Create?Date:?2021/08/08?16:36:01
//?Design?Name:?
//?Module?Name:?detect
//?Project?Name:?
//?Target?Devices:?
//?Tool?Versions:?
//?Description:?
//?
//?Dependencies:?
//?
//?Revision:
//?Revision?0.01?-?File?Created
//?Additional?Comments:
//?
//////////////////////////////////////////////////////////////////////////////////
module?detect(
input?clk,
input?x,
output?reg?z,
output??reg?[7:0]?Z
????);
????parameter??S0?=8'b0000000_01;????????
????parameter??S1?=8'b0000000_10;
????parameter??S2?=8'b0000001_00;
????parameter??S3?=8'b0000010_00;
????parameter??S4?=8'b0000100_00;
????parameter??S5?=8'b0001000_00;
????parameter??S6?=8'b0010000_00;
????parameter??S7?=8'b0100000_00;
????parameter??S8?=8'b1000000_00;
????reg?[7:0]?CS;
????reg?[7:0]?NS?=?S0;
????
????????always?@(posedge?clk)?begin
????????CS?<=?NS;
????
????end
????????
????????always?@(*)?begin
????????????case(CS)
????????????S0:?NS=(x==1)??S1:S0;
????????????S1:?NS=(x==1)??S2:S0;
????????????S2:?NS=(x==0)??S3:S2;
????????????S3:?NS=(x==1)??S4:S0;
????????????S4:?NS=(x==0)??S5:S2;
????????????S5:?NS=(x==1)??S6:S0;
????????????S6:?NS=(x==1)??S7:S0;
????????????S7:?NS=(x==0)??S8:S2;
????????????S8:?NS=(x==1)??S4:S0;
????????????default:???NS?=?S0;
????????????endcase
????????
????????
????????end
????????
????????//根据现态或次态?输出
????????always?@(posedge?clk)?begin
????????????if(NS==S8)
????????????????z<=1'b1;
????????????else
????????????????z<=1'b0;
????????end

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=1114